Index: drivers/net/acenic.c =================================================================== RCS file: /var/cvs/linux/drivers/net/acenic.c,v retrieving revision 1.2 diff -u -p -r1.2 acenic.c --- drivers/net/acenic.c 25 Jan 2002 20:14:54 -0000 1.2 +++ drivers/net/acenic.c 2 Apr 2002 19:34:20 -0000 @@ -819,10 +819,13 @@ static void __exit ace_module_cleanup(vo if (ap->version >= 2) writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl); + readl(®s->CpuCtrl); /* GGG flush write */ + /* * This clears any pending interrupts */ writel(1, ®s->Mb0Lo); + readl(®s->Mb0Lo); /* GGG flush write */ /* * Make sure no other CPUs are processing interrupts @@ -1094,35 +1097,28 @@ static int __init ace_init(struct net_de * to any crashes involving the NIC */ writel(HW_RESET | (HW_RESET << 24), ®s->HostCtrl); - wmb(); + wmb(); readl(®s->HostCtrl); /* GGG flush write */ + mdelay(1); /* - * Don't access any other registes before this point! + * Don't access any other registers before this point! */ -#ifdef __BIG_ENDIAN /* * This will most likely need BYTE_SWAP once we switch * to using __raw_writel() */ -#ifdef __parisc__ - writel((WORD_SWAP | BYTE_SWAP | CLR_INT | - ((WORD_SWAP | BYTE_SWAP | CLR_INT) << 24)), - ®s->HostCtrl); -#else - writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)), - ®s->HostCtrl); -#endif -#else writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)), ®s->HostCtrl); -#endif - mb(); + mb(); readl(®s->HostCtrl); /* GGG flush write */ /* * Stop the NIC CPU and clear pending interrupts */ writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl); + readl(®s->CpuCtrl); /* GGG flush write */ + writel(0, ®s->Mb0Lo); + readl(®s->Mb0Lo); /* GGG flush write */ tig_ver = readl(®s->HostCtrl) >> 28; @@ -1141,6 +1137,7 @@ static int __init ace_init(struct net_de tig_ver, tigon2FwReleaseMajor, tigon2FwReleaseMinor, tigon2FwReleaseFix); writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl); + readl(®s->CpuBCtrl); /* GGG flush write */ /* * The SRAM bank size does _not_ indicate the amount * of memory on the card, it controls the _bank_ size! @@ -1171,7 +1168,7 @@ static int __init ace_init(struct net_de writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, ®s->ModeStat); #endif - mb(); + mb(); readl(®s->ModeStat); /* GGG flush write */ mac1 = 0; for(i = 0; i < 4; i++) { @@ -1308,7 +1305,7 @@ static int __init ace_init(struct net_de tmp &= ~DMA_READ_WRITE_MASK; tmp |= DMA_READ_MAX_128; /* - * All the docs sy MUST NOT. Well, I did. + * All the docs say MUST NOT. Well, I did. * Nothing terrible happens, if we load wrong size. * Bit w&i still works better! */ @@ -1317,6 +1314,12 @@ static int __init ace_init(struct net_de writel(tmp, ®s->PciState); #if 0 +/* The Host PCI bus controller driver has to set FBB. + * If all devices on that PCI bus support FBB, then the controller + * can enable FBB support in the Host PCI Bus controller (or on + * the PCI-PCI bridge if that applies). + * -ggg + */ /* * I have received reports from people having problems when this * bit is enabled. @@ -1385,6 +1388,7 @@ static int __init ace_init(struct net_de memset(ap->skb, 0, sizeof(struct ace_skb)); ace_load_firmware(dev); + ap->fw_running = 0; tmp_ptr = ap->info_dma; @@ -1396,9 +1400,9 @@ static int __init ace_init(struct net_de set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma); info->evt_ctrl.flags = 0; - set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma); *(ap->evt_prd) = 0; - wmb(); + set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma); + writel(0, ®s->EvtCsm); set_aceaddr(&info->cmd_ctrl.rngptr, 0x100); @@ -1508,9 +1512,9 @@ static int __init ace_init(struct net_de writel(DMA_THRESH_8W, ®s->DmaWriteCfg); #endif - writel(0, ®s->MaskInt); writel(1, ®s->IfIdx); - writel(1, ®s->AssistState); + writel(0, ®s->MaskInt); + readl(®s->MaskInt); /* GGG flush write */ writel(DEF_STAT, ®s->TuneStatTicks); writel(DEF_TRACE, ®s->TuneTrace); @@ -1601,6 +1605,7 @@ static int __init ace_init(struct net_de writel(tigon2FwStartAddr, ®s->Pc); writel(0, ®s->Mb0Lo); + readl(®s->Mb0Lo); /* GGG flush write */ /* * Set tx_csm before we start receiving interrupts, otherwise @@ -1620,10 +1625,21 @@ static int __init ace_init(struct net_de */ memset(&ap->stats, 0, sizeof(ap->stats)); + /* + * Enable DMA engine now. + * If we do this sooner, Mckinley box pukes. + * I assume it's because Tigon II DMA engine wants to check + * *something* even before the CPU is started. + */ + writel(1, ®s->AssistState); /* enable DMA */ + readl(®s->AssistState); /* GGG flush write */ + mdelay(1); + /* * Start the NIC CPU */ writel(readl(®s->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), ®s->CpuCtrl); + readl(®s->CpuCtrl); /* GGG flush write */ /* * Wait for the firmware to spin up - max 3 seconds. @@ -1636,6 +1652,7 @@ static int __init ace_init(struct net_de ace_dump_trace(ap); writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl); + readl(®s->CpuCtrl); /* GGG flush write */ /* aman@sgi.com - account for badly behaving firmware/NIC: * - have observed that the NIC may continue to generate @@ -1650,6 +1667,7 @@ static int __init ace_init(struct net_de writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl); writel(0, ®s->Mb0Lo); + readl(®s->Mb0Lo); /* GGG flush write */ ecode = -EBUSY; goto init_error; @@ -2312,6 +2330,7 @@ static void ace_interrupt(int irq, void * threads and it is wrong even for that case. */ writel(0, ®s->Mb0Lo); + readl(®s->Mb0Lo); /* GGG flush write */ /* * There is no conflict between transmit handling in @@ -3072,6 +3091,7 @@ int __init ace_load_firmware(struct net_ tigon2FwRodataLen); ace_copy(regs, tigon2FwData, tigon2FwDataAddr,tigon2FwDataLen); } + readl(®s->CpuCtrl); /* GGG flush write */ return 0; } @@ -3096,23 +3116,24 @@ static void __init eeprom_start(struct a { u32 local; + mb(); readl(®s->LocalCtrl); /* GGG flush write */ udelay(ACE_SHORT_DELAY); local = readl(®s->LocalCtrl); local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE; writel(local, ®s->LocalCtrl); - mb(); + mb(); readl(®s->LocalCtrl); /* GGG flush write */ udelay(ACE_SHORT_DELAY); local |= EEPROM_CLK_OUT; writel(local, ®s->LocalCtrl); - mb(); + mb(); readl(®s->LocalCtrl); /* GGG flush write */ udelay(ACE_SHORT_DELAY); local &= ~EEPROM_DATA_OUT; writel(local, ®s->LocalCtrl); - mb(); + mb(); readl(®s->LocalCtrl); /* GGG flush write */ udelay(ACE_SHORT_DELAY); local &= ~EEPROM_CLK_OUT; writel(local, ®s->LocalCtrl); - mb(); + mb(); readl(®s->LocalCtrl); /* GGG flush write */ } @@ -3126,7 +3147,7 @@ static void __init eeprom_prep(struct ac local &= ~EEPROM_DATA_OUT; local |= EEPROM_WRITE_ENABLE; writel(local, ®s->LocalCtrl); - mb(); + mb(); readl(®s->LocalCtrl); /* GGG flush write */ for (i = 0; i < 8; i++, magic <<= 1) { udelay(ACE_SHORT_DELAY); @@ -3135,16 +3156,16 @@ static void __init eeprom_prep(struct ac else local &= ~EEPROM_DATA_OUT; writel(local, ®s->LocalCtrl); - mb(); + mb(); readl(®s->LocalCtrl); /* GGG flush write */ udelay(ACE_SHORT_DELAY); local |= EEPROM_CLK_OUT; writel(local, ®s->LocalCtrl); - mb(); + mb(); readl(®s->LocalCtrl); /* GGG flush write */ udelay(ACE_SHORT_DELAY); local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT); writel(local, ®s->LocalCtrl); - mb(); + mb(); readl(®s->LocalCtrl); /* GGG flush write */ } } @@ -3157,18 +3178,18 @@ static int __init eeprom_check_ack(struc local = readl(®s->LocalCtrl); local &= ~EEPROM_WRITE_ENABLE; writel(local, ®s->LocalCtrl); - mb(); + mb(); readl(®s->LocalCtrl); /* GGG flush write */ udelay(ACE_LONG_DELAY); local |= EEPROM_CLK_OUT; writel(local, ®s->LocalCtrl); - mb(); + mb(); readl(®s->LocalCtrl); /* GGG flush write */ udelay(ACE_SHORT_DELAY); /* sample data in middle of high clk */ state = (readl(®s->LocalCtrl) & EEPROM_DATA_IN) != 0; udelay(ACE_SHORT_DELAY); - mb(); + mb(); readl(®s->LocalCtrl); /* GGG flush write */ writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl); - mb(); + mb(); readl(®s->LocalCtrl); /* GGG flush write */ return state; } @@ -3223,7 +3244,7 @@ static int __init read_eeprom_byte(struc regs = ((struct ace_private *)dev->priv)->regs; /* - * Don't take interrupts on this CPU will bit banging + * Don't take interrupts on this CPU while bit banging * the %#%#@$ I2C device */ __save_flags(flags); @@ -3271,12 +3292,14 @@ static int __init read_eeprom_byte(struc local = readl(®s->LocalCtrl); local &= ~EEPROM_WRITE_ENABLE; writel(local, ®s->LocalCtrl); + readl(®s->LocalCtrl); /* GGG flush write */ udelay(ACE_LONG_DELAY); mb(); local |= EEPROM_CLK_OUT; writel(local, ®s->LocalCtrl); - mb(); + readl(®s->LocalCtrl); /* GGG flush write */ udelay(ACE_SHORT_DELAY); + mb(); /* sample data mid high clk */ result = (result << 1) | ((readl(®s->LocalCtrl) & EEPROM_DATA_IN) != 0); @@ -3285,11 +3308,13 @@ static int __init read_eeprom_byte(struc local = readl(®s->LocalCtrl); local &= ~EEPROM_CLK_OUT; writel(local, ®s->LocalCtrl); + readl(®s->LocalCtrl); /* GGG flush write */ udelay(ACE_SHORT_DELAY); mb(); if (i == 7) { local |= EEPROM_WRITE_ENABLE; writel(local, ®s->LocalCtrl); + readl(®s->LocalCtrl); /* GGG flush write */ mb(); udelay(ACE_SHORT_DELAY); } @@ -3297,12 +3322,12 @@ static int __init read_eeprom_byte(struc local |= EEPROM_DATA_OUT; writel(local, ®s->LocalCtrl); - mb(); + mb(); readl(®s->LocalCtrl); /* GGG Flush write */ udelay(ACE_SHORT_DELAY); writel(readl(®s->LocalCtrl) | EEPROM_CLK_OUT, ®s->LocalCtrl); udelay(ACE_LONG_DELAY); writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl); - mb(); + mb(); readl(®s->LocalCtrl); /* GGG Flush write */ udelay(ACE_SHORT_DELAY); eeprom_stop(regs);